Crossbar Arbiter Architecture for High-Speed MAPOS Switch

This paper describes a crossbar-switch arbiter for a high-speed MAPOS switch. The arbiter uses the following techniques suitable for variable-length frame switching: 1. parallel processing for handling requests from network interfaces and for resource allocation, 2. techniques such as release-on-request, fast back-to-back transfer, and request prefetching to reduce the arbitration overhead, and 3. a resource sampling technique to enable efficient one-shot multicast processing. Our simulationbased performance evaluation and estimation of the scale of its logic circuits indicated that this arbiter can be implemented through simple hardware. key words: MAPOS, high-speed switch, crossbar, arbiter